The present invention relates generally to semiconductor device processing and, more particularly, to a two-sided chemical mechanical polishing pad for semiconductor processing.
Many electronic and computer-related products such as semiconductors, hard disks and CD-ROMS require highly polished or planarized surfaces in order to achieve optimum performance. In the semiconductor manufacturing industry, for example, silicon workpieces are used in the manufacture of integrated circuit components and the like. The workpieces are known in the industry as “wafers” and typically have a flat, circular disk-like shape. The wafers are initially sliced from a silicon ingot and, thereafter, undergo multiple masking, etching, and layer (e.g., dielectric and conductor) deposition processes to create microelectronic structures and circuitry on the wafers. The surface of a wafer undergoing these processes is typically polished or planarized between processing steps to ensure proper flatness, thereby permitting use of subsequent photolithographic processes for building additional dielectric and metallization layers on the wafer surface.
Accordingly, chemical mechanical planarization or Polishing (CMP) machines have been developed to planarize or polish silicon wafer surfaces to a flat condition suitable for manufacture of integrated circuit components and the like. More specifically, CMP is a manufacturing process performed by a polishing pad in combination with a polishing fluid (slurry) to polish, for example, a silicon wafer having metal circuits embedded in trenches in a substrate of the wafer. The polishing pad is mounted on a platen of a known polishing apparatus. A base pad is positioned between the polishing pad and the platen.
A conventional base pad is formed from foamed sheets or felts impregnated with a polymeric material. However, such a base pad is too compliant when subjected to the forces occurring during a polishing operation, which can cause the pad to settle into recesses in the substrate that is being polished, which, in turn, causes excessive polishing. As a result, the surfaces of the embedded circuits become polished excessively, causing unwanted recesses known as dishing. Further, such a base pad absorbs polishing fluid, and is compressed during a polishing operation such that it becomes deformed in all directions, causing the pad to become too compliant. A measure of the compressibility in such different directions provides a prediction that the base pad will deform in such different directions due to the application of forces.
Consequently, as a result of problems such as wafers sticking to pads at the end of the CMP run (resulting from surface tension between the wafer and the pad), a second pad has been used underneath the first pad, wherein the first pad is perforated entirely there through while the second pad includes a plurality of grooves or channels. However, by using separate first and second pads, there is an additional cost associated therewith. Moreover, when the first and second pads are manually aligned (as is done in the conventional manner), the possibility arises that the perforations (holes) in the first pad do not all align with a corresponding groove in the second pad. This, in turn, may have an adverse impact on process yield variations.